Yield - Performance Tradeoffs for VLSI Processors with Partially Good Two-Level On-Chip Caches
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چکیده
In this paper a yield model for single chip VLSI processors with two level on-chip caches is derived. Using this model and trace tiven simulations the distribution of the faulty cache blocks into the first and second level caches can be determined so as to achieve a significant yield enhancement with the min imum performance degradation.
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تاریخ انتشار 1996